ALI M Memory Cache and DRAM Controller

The M1521 provides the system controller and data path components for the Extensa 900 Pentium-based system. It provides 64-bit CPU bus interface, 32-bit PCI bus interface, 64/72 DRAM data bus with ECC or parity, secondary cache interface including pipeline burst SRAM or asynchronous SRAM, PCI master to DRAM interface, four PCI master arbiters, and a UMA arbiter. The M1521 bus interfaces are designed to interface with 3V and 5V buses. It directly connects to 3 V CPU bus, 3V or 5V tag, 3V or 5V DRAM bus, and 5V PCI bus. Features of the ALI M1521

  • Supports all Intel/Cyrix®/AMD 586-class processors (with host bus of 66 MHz, 60 MHz and 50 MHz at 3V)
  • Supports M1/K5/Dakota™ CPUs
  • Supports linear wrap mode for M1
  • Supports asynchronous/pipeline-burst SRAM
  • Write-back/dynamic write-back cache policy
  • Built-in 8K* 2-bit SRAM for MESI protocol to cost and enhance performance
  • Cacheable memory up to 512 MB with 11-bit tag SRAM
  • Supports 3V/5V SRAMs for tag address
  • RAS lines
  • 64-bit data path to memory
  • Symmetrical/asymmetrical DRAMs
  • 3V or 5V DRAMs
  • Duplicated MA[1:0] driving pins for burst access
  • No buffer needed for RASJ and CASJ and MA[1:0]
  • CBR and RAS-only refresh
  • Supports 64M-bit (16M* 4, 8M* 8, 4M*16) technology DRAMs
  • Supports programmable-strength MA buffer
  • Supports error checking and correction (ECC) and parity for DRAM
  • Supports the most flexible six 32-bit populated banks of DRAM (to spare 12 MB for Windows 95)
  • Supports SIMM and DIMM
  • UMA (unified memory architecture)
  • Dedicated UMA arbiter pins
  • Supports several protocols from major graphics vendors
  • SFB size : 512 KB/1 MB/2 MB/3 MB/4 MB
  • CPU could access frame buffer memory through system memory controller
  • Alias address for frame buffer memory
  • Fully synchronous 25/30/33 MHz 5V PCI interface
  • PCI bus arbiter: five PCI masters and M1523 supported
  • DWORDs for CPU-to-PCI Memory write posted buffers
  • Convert back-to-back CPU to PCI memory write to PCI burst cycle
  • DWORDS for PCI-to-DRAM write-posted/Read-prefetching buffers
  • PCI-to-DRAM up to 133 MB/sec bandwidth (even when L1/L2 write-back)
  • L1/L2 pipelined snoop ahead for PCI-to-DRAM cycle
  • Supports PCI mechanism #1 only
  • PCI spec. 2.1 support (N(16/8)+8 rule, passive release, fair arbitration)
  • Enhanced performance for memory-read-line, memory-read-multiple, and memory-write-multiple
  • Invalidates PCI commands
  • DRAM refresh during 5V system suspend
  • I/O leakage stopper for power saving during system suspend ALI M1523 (PCI-ISA Bridge)

The M1523 provides a bridge between the PCI bus and the ISA bus and ensures full compatibility between the PCI and ISA functions. The M1523 has an Integrated System Peripherals (ISP) chip that provides advanced DMA controller features. This chip contains the keyboard controller, real time clock and IDE master controller. This chip also supports the Advanced Programmable Interrupt controller (APIC) interface.

One eight-byte bidirectional line buffer is provided for ISA/DMA master memory read/ writes. One 32-bit wide posted-write buffer is provided for PCI memory write cycles to the ISA bus. It also supports a PCI to ISA IRQ routing table and level-to-edge trigger transfer.

The chip has two extra IRQ lines and one programmable chip select for motherboard Plug-and-Play functions. The interrupt lines can be routed to any of the available ISA interrupts.

The on-chip IDE controller supports two IDE connectors for up to four IDE devices providing an interface for IDE hard disks and CD-ROMs. The ATA bus pins are dedicated to improve the performance of IDE master.

The M1523 supports the Super Green feature for Intel and Intel compatible CPUs. It implements programmable hardware events, software event and external switches (for suspend/turbo/ring-in). The M1523 provides CPU clock control (STPCLKJ). The STPCLKJ can be active (low) or inactive (high) in turn by throttling control. M1523 Features Summary

  • Provides a bridge between the PCI bus and ISA bus
  • PCI interface
  • Supports PCI master and slave interface
  • Supports PCI master and slave initiated termination
  • PCI spec. 2.1 compliant (delay transaction support)
  • Buffers
  • 8-byte bidirectional line buffers for DMA/ISA memory read/write cycles to PCI bus
  • 32-bit posted-write buffer for PCI memory write and I/O data write (for sound card) to ISA bus
  • Provides steerable PCI interrupts for PnP PCI devices
  • Up to eight PCI interrupts routing
  • Level-to-edge trigger transfer
  • Enhanced DMA controller
  • Provides seven programmable channels (four for 8-bit data size, three for 16-bit data size)
  • 32-bit addressability
  • Provides compatible DMA transfers
  • Provides type F transfers
  • Interrupt controller
  • Provides 14 interrupt channels
  • Independently programmable level/edge triggered channels
  • Counter/Timers
  • Provides 8254 compatible timers for system timer, refresh request, speaker output use
  • Keyboard controller
  • Built-in PS2/AT keyboard controller
  • The specific I/O is used to save the external TTL buffer
  • Real time clock
  • Built-in real time clock
  • 128-byte CMOS RAM with 2
  • Plug-and-Play port support
  • Programmable chip select
  • Steerable interrupt request lines
  • PMU interface
  • Supports CPU SMM mode, SMI feature
  • Supports programmable stop clock throttle
  • Supports the APM control
  • Provides external suspend mode switch/turbo switch/ring-in switch
  • Provides four system states for power saving (on, doze, standby, suspend)
  • Provides three timers from 1 second to 300 minutes to individually monitor VGA, MODE, IN status
  • Supports RTC alarm wake up control
  • IDE interface
  • Built-in PCI IDE master controller
  • Supports PIO modes up to mode 5 timings, and multiword DMA mode 0, 1, 2
  • 8 x 32-bit pre-read and posted-write buffers
  • Dedicated pins for ATA interface
  • Supports up to 256 KB ROM size decode
  • Reserved USB interface
  • 208-pin PQFP package

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