Main Memory Controller

M1523

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IRQ12 — § MSCLK KBDATA KBCLK/KBCSJ KBINH/IRQ1 IDESCS3J IDESCS1J IDEPCS3J IDEPCS1J IDE_A0 IDE_A2 IDE_A1 IDAKJ1 IDAKJ0 IDERDY IDEIORJ IDEIOWJ IDRQ1 IDRQ0 IDE_D0 IDE_D15 Vss IDE_D1 IDE_D14 IDE_D2 IDE_D13 IDE_D3 IDE_D12 IDE_D4 IDE_D11 IDE_D5 IDE_D10 IDE_D6 IDE_D9 IDE_D7 VDD IDE_D8 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 CBEJ0 AD8 AD9 AD10 AD11 VDD

156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105

Figure 4-5 M1523 Pinouts

4.3.2.2 ALI M6377 (Power Management Unit)

  • Three operation states
  • ON state
  • DOZE state
  • SLEEP state
  • Programmable DOZE and SLEEP timers
  • Programmable EL timer for backlight control
  • Three output pins depending on operation state, each pin is programmable and power configurable.
  • Provide system activity monitoring, including:

video hard disk floppy disk serial port keyboard parallel port two programmable I/O groups activity monitor, each group contains 16/8 I/O addresses. one predefined I/O group activity monitor

Multiple external wake up events from DOZE and SLEEP states

  • External push button
  • RTC alarm

Two levels battery warning monitor AC power monitoring to disable PMU function

A simplified block diagram of the M6377 Power Management Unit is provided in Figure 4-6. The chip pinouts are provided in Figure 4-7.

Electric Diagram Acer Extensa 5235
Figure 4-6 M6377 Simplified Block Diagram

Figure 4-7 M6377 Chip Pinouts

4.3.2.4 C&T 65550 High Performance Flat Panel / CRT VGA Controller

The C&T65550 of high performance multimedia flat panel / CRT GUI accelerators extend CHIPS' offering of high performance flat panel controllers for full-featured note books and sub-notebooks. The C&T65550 offers 64-bit high performance and new hardware multimedia support features.

HIGH PERFORMANCE

Based on a totally new internal architecture, the C&T65550, integrates a powerful 64-bit graphics accelerator engine for Bit Block Transfer (BitBLT), hardware cursor, and other functions intensively used in graphical User Interfaces (GUls) such as Microsoft Windows™. Superior performance is also achieved through a direct 32-bit interface to the PCI Local Bus. The C&T65550 offers exceptional performance when combined with CHIPS advanced linear acceleration driver technology .

HARDWARE MULTIMEDIA SUPPORT

The C&T65550 implements independent multimedia capture (and display systems on-chip. The capture system places data in display memory (usually off screen) and the display system places it in a window on the screen.

The capture system can receive data from either the system bus or from the ZV enabled video port in either RGB or YUV format. The input data can also scaled down before storage in display memory (c.g., from any size larger than 320x240 down to 352x248). Capture of input data may also be double buffered for smoothing and to prevent image tearing.

The display system can independently place either RGB or YUV data from any where in display memory into an on-screen window which can be any size and located at any pixel boundary (YUV data is converted to RGB "on-the-fly" on out put). Non-rectangular windows .are supported via color keying. The data can be functionally zoomed on output up to 8x to fit the onscreen window and can be horizontally and vertically inter polated to scale or zoom artifacts. Interlaced and non-interlaced data are supported in both capture and display systems.

VERSATILE PANEL SUPPORT

The C&T65550 supports a wide variety of monochrome and color Single-Panel, Single-Drive (SS) and Dual-Panel, Dual Drive (DD) standard and high-resolution passive STN and active matrix TFT/MIM LCD, and EL panels. For monochrome panels, up to 64 gray scales are supported. Up to 4096 different colors can be displayed on passive STN LCDs and up to 16M colors on 24-bit active matrix LCDs.

LOW POWER CONSUMPTION

The C&T65550 employs a variety of advanced power management features to reduce power consumption of the display sub-system and extend battery life. Although optimized for 3.3V operation, The C&T65550 controller's internal logic. memory interface, bus interface, and panel interfaces can he independently configured to operate at either 3.3V or 5V.

SOFTWARE COMPATIBILITY/FLEXIBILITY

The C&T65550 are fully compatible with VGA at the register, and BIOS levels. CHIPS and third-party vendors supply fully VGA-compatible BIOS, end-user utilities and drivers for common application programs

Pin names in parentheses (...) indicate alternate functions.

A simplified block diagram of the C&T65550 is shown in Figure 4-8.

A simplified block diagram of the C&T65550 is shown in Figure 4-8.

Vga Block Diagram
Figure 4-8 C&TG5550 Simplified Block Diagram

4.3.2.5 TI1130 PCMCIA Controller

The Tl PCI1130 is a high-performance PCI-to-PC Card controller that supports two independent PC Card sockets compliant with the 1995 PC card standard. The PCI1130 provides a set of features that make it ideal for bridging between PCI and PC Cards in both notebook and desktop computers. The 1995 PC Card standard retains the 16-bit PC Card specification defined in PCMCIA release 2.1 and defines the new 32bit PC Card, called CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1130 supports any combination of 16-bit and CardBus PC Cards in its two sockets, powered at 3.3 V or 5 V as required. The PCI 1130 is compliant with the PCI local bus specification revision 2.1, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers or CardBus PC Card bus mastering cycles.

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1130 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent 32-bit write buffers allow fast-posted writes to improve system-bus utilization.

An advanced CMOS process is used to achieve low system-power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes allow the host power-management system to further reduce power consumption.

A simplified block diagram of the PCMCIA Controller is shown in Figure 4-9.

Block Diagram Cells Aspire 9420
Figure 4-9 PCMCIA Controller, Simplified Block Diagram

4.3.2.6 NS87336VJG Super I/O Controller

The PC87336VJG is a single chip solution for most commonly used I/O peripherals in ISA, and EISA based computers. It incorporates a Floppy Disk Controller(FDC), two full featured UARTs, and an IEEE 1284 compatible parallel port Standard PC-AT address decoding for all the peripherals and a set of configuration registers are also implemented in this highly integrated member of the Super l/O family. Advanced power management features, mixed voltage operation and integrated Serial-lnfrared(both IrDA and Sharp) support makes the PC87336 an ideal choice for low-power and/or portable personal computer applications.

The PC87336 FDC uses a high performance digital data separator eliminating the need for any external filter components. It is fully compatible with the PC8477 and incorporates a superset of DP8473, NEC PD765 and N82077 floppy disk controller functions. All popular 5.25' and 3.5' floppy drives, including the 2.88 MB 3.5' floppy drive, are supported. In addition, automatic media sense and 2 Mbps tape drive support are provided by the FDC.

The two UARTs are fully NS16450 and NS16550 compatible. Both ports support MIDI baud rates and one port also supports IrDAs the HP SIR and Sharp SIR compliant signaling protocol. The parallel port is fully IEEE 1284 level 2 compatible. The SPP(Standard Parallel Port) is fully compatible wit ISA and EISA parallel ports. In addition to the SPP, EPP(Enhanced Parallel Port) and ECP(Extended Capabilities Port) modes are supported by the parallel port.

A set of configuration registers are provided to control the Plug and Play and other various functions of the PC87336. These registers are accessed using two 8-bit wide index and data registers. The ISA I/O address of the register pair can be relocated using a power-up strapping option and the software configuration after power-up.

When idle, advanced power management features allows the PC87336 to enter extremely low power modes under software control. The PC87336 car operate from a 5V or a 3.3V power supply. An unique I/O cell structure allows the PC87336 to interface directly with 5 V external components while operating from a 3.3 V power supply.

Some of the major features include:

  • 100% compatible with ISA, and EISA architectures
  • The Floppy Disk Controller:
  • Software compatible with the DP8473, the 765A and the N82077
  • 16-byte FlFO (disabled by default)
  • Burst and Non-Burst modes
  • Perpendicular Recording drive support
  • New high-performance internal digital data separator(no external filter components required)
  • Low-power CMOS with enhanced power-down mode
  • Automatic media-sense support, with full IBM TDR(Tape Drive Register) implementation
  • Supports fast 2 Mbps and standard 1 Mbps/500 kbps/250 kbps tape drives
  • Parallel Port
  • Enhanced Parallel Port(EPP) compatible
  • Extended Capabilities Port(ECP) compatible, including level 2 support
  • Bidirectional under either software or hardware control
  • Compatible with ISA, and EISA, architectures
  • Ability to multiplex FDC signals on parallel port pins allows use of an external Floppy Disk Drive(FDD)
  • Includes protection circuit to prevent damage to the parallel port when a connected printer is powered up or is operated at a higher voltage
  • The UARTs:
  • Software compatible with the PC16550A and PC16450
  • MIDI baud rate support
  • Infrared support on UART2(IrDA and Sharp-compliant)
  • The Address Decoder
  • 6 bit or 10 bit decoding
  • External Chip Select capability when 10 bit decoding
  • Full relocation capability(No limitation)
  • Enhanced Power Management
  • Special configuration registers for power-down
  • Enhanced programmable power-down FDC command
  • Auto power-down and wake-up modes
  • 2 special pins for power management
  • Typical current consumption during power-down is less than 10 uA
  • Reduced pin leakage current
  • Mixed Voltage support
  • Supports standard 5 V operation
  • Supports 3.3 V operation
  • Supports mixed internal 3.3V operation with 3.3V/5V external configuration
  • The General Purpose Pins:
  • 2 pins The Bidirectional Parallel Port:, for 2 separate programmable chip select decoders, can be programmed for game port control
  • Plug and Play Compatible:
  • 16 bit addressing(full programmable)
  • 10 selectable IRQs
  • 3 selectable DMA Channels
  • 3 SIRQ Inputs allows external devices to mapping IRQs 100-Pin TQFP package - PC87336VJG

A simplified block diagram of the Super I/O controller is provided in Figure 4-10.

Config. Inputs

I/O Ports

Serial Interrupt Serial Interrupt IR

Interface y Interface Interface

Configuration Registers

General Purpose Registers

Control

Serial Interrupt Serial Interrupt IR

Interface y Interface Interface

Floppy Drive

Control

Interrupt and DMA

Floppy Drive

Hifh Current Driver

Interrupt Data Handshake

Interrupt and DMA

Figure 4-10 Super I/O Controller Block Diagram

4.3.2.6 ESS1688 Audio Controller

ESS Technology has developed the ES1688 AudioDrive®, a single chip solution for adding 16-bit stereo audio and four-operator FM music synthesis to personal computers. It has integrated all the major blocks of audio in to a single chip that can be designed into a motherboard, notebook PC, add-on card, or integrated onto other peripheral cards such as VGA, LAN, I/O, etc. The ES1688 AudioDrive can record, compress, and playback voice, sound and music with built-in mixer controls. It consists of an embedded microprocessor, 16-bit stereo A/D and D/A, 20-voice FM music synthesizer, MIDI serial port compatible with MPU401 UART mode, DMA control, and ISA bus interface logic. A DSP serial interface allows an external DSP to take over analog resources such as the D/A or A/D converters. Control of I/O address, DMA, and interrupt selection can be by jumper or by control of system software. Interface to analog inputs is extremely simple. There are stereo inputs for CD-audio, line-in, and an external music synthesis chip, and a mono microphone input to an internal pre-amp. A digital PC speaker input is converted to an analog signal with volume control and is available as an analog output signal. Address decode outputs simplify interfacing to a game port. Advanced power management features such as Suspend/Resume and partial power-down are supported. The ES1688 AudioDrive is compatible with Sound Blaster PRO™ version 3.01 voice and music functions as documented in the Sound Blaster Series Developer Kit. The ES1688 is pin-compatible with the ES688 AudioDrive.

Sound Blaster Model 4520

Figure 4-11 ES1688 Sound Chip Block Diagram

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