Core POST Code Table

POST Code

Function

Phase

Component

0x00

Early Microcode update for CAR

CEI / SEC

Core

0x01

Enable CAR

CEI / SEC

Core

0x02

CAR Done, initial stack

CEI / SEC

Core

0xEE

unknown CPU ID to load uCode

CEI / SEC

CPU

0xEF

unknown DT CPU to load uCode

CEI / SEC

CPU

0xnn

File count found in a volume

PEI

Core

0x11

Debug Test driver for debug test PPI 1 (If install debugTest driver)

PEI

Core

0x22

Debug Test driver for debug test PPI 2 (If install debugTest driver)

PEI

Core

0x33

Debug Test driver for debug test PPI 3 (If install debugTest driver)

PEI

Core

0x44

Entry point of loadfile

PEI

Core

0x88

Entry point of apMuLoader

PEI

Core

0x80

A PEIM found

PEI

Core

0x82

PEIM not dispatched yet

PEI

Core

0x84

PEIM satisfies depex

PEI

Core

0x86

Image loaded but fail on security

PEI

Core

0x88

Executing a PEIM

PEI

Core

0x8A

Processing notify event for newly installed PPI

PEI

Core

0x8C

Handing off to next phase (DXE)

PEI

Core

0x8F

Fail to hand off to next phase, system halt

PEI

Core

0x90

All PEIM dispatched! Going to DxeIpl

PEI

Core

0xCC

AP Micro-code update

PEI

Core

0x20

S3 resume entry

S3 resume

Core

0x21

Start running Boot-time bootscripts

S3 resume

Core

0x22

Start running Run-time bootscripts

S3 resume

Core

0x23

End of S3 resume, jump back to Waking vector

S3 resume

Core

0x80

Initialize the chipset

Crisis Recovery

Core

0x81

Initialize the bridge

Crisis Recovery

Core

0x82

Initialize the CPU

Crisis Recovery

Core

0x89

Set Huge Segment

Crisis Recovery

Core

0x83

Initialize system timer

Crisis Recovery

Core

0x84

Initialize system I/O

Crisis Recovery

Core

0x88

Initialize Multi Processor

Crisis Recovery

Core

0x8A

Initialize OEM special code

Crisis Recovery

Core

0x8B

Initialize PIC and DMA

Crisis Recovery

Core

0x8C

Initialize Memory type

Crisis Recovery

Core

0x8D

Initialize Memory size

Crisis Recovery

Core

0x8F

Initialize SMM

Crisis Recovery

Core

0x90

System memory test

Crisis Recovery

Core

POST Code

Function

Phase

Component

0x91

Initialize interrupt vectors

Crisis Recovery

Core

0x92

Initialize Run Time Clock

Crisis Recovery

Core

0x99

Initialize security

Crisis Recovery

Core

0x93

Initialize video

Crisis Recovery

Core

0x94

Output one beep

Crisis Recovery

Core

0x98

USB Initialization

Crisis Recovery

Core

0x95

Initialize the installed boot devices

Crisis Recovery

Core

0x96

Clear Huge segment

Crisis Recovery

Core

0x97

Boot Crisis Disk

Crisis Recovery

Core

0x20

DXE starts

DXE

Core

0x30

BIOSPSM

DXE

Core

0x02

BIOSBlockIO

DXE

Core

0x00

BIOSPSM Exception Handler / Divide error

BIOSPSM

Core

0x38

Cannot locate LegacyRegion DXE

BIOSPSM

Core

0xB1

ACPISupport driver Installed

DXE

Core

0xE0

BDS Entry

DXE

Core

0x07

IA32 variable driver entry

DXE

Core

0x0D

conspliter driver entry

DXE

Core

0x10

partition driver entry

DXE

Core

0x49

pciRootBridge driver entry

DXE

Core

0xC6

pciBusDriver entry

DXE

Core

0xE0

Go to legacy BIOS or BDS Entry Point

DXE

Core

0x90

Start Image

DXE

Core

0x90

Start Image Successfully

DXE

Core

0x90

Start Image Failed

DXE

Core

0x33

Debug Test driver for debug test PPI 1

DXE

Core

0x22

Debug Test driver for debug test PPI 2

DXE

Core

0x11

Debug Test driver for debug test PPI 3

DXE

Core

0x02

Invalid event # for measuring Separator Event

DXE

TCG

0x02

Invalid event # for measuring Separator Event

DXE

TCG

0x02

PCR Index over limit (PCR > 23)

DXE

TCG

0x02

TCG copy memory failed

DXE

TCG

0x09

TCG log event failed

DXE

TCG

0x09

Setup event log failed

DXE

TCG

0x12

TIS set active locality failed

DXE

TCG

0x12

TIS relinquish active locality failed

DXE

TCG

0x12

TIS wait command ready failed (prepare to send)

DXE

TCG

0x12

TIS abort 'send 'command due to timeout

DXE

TCG

0x12

TIS abort 'sendAndGo 'command due to timeout

DXE

TCG

0x04

TIS wait bit set failed before send last byte

DXE

TCG

0x12

TIS abort command due to timeout before send last byte

DXE

TCG

0x04

TIS wait bit clear failed when sending last byte

DXE

TCG

POST Code

Function

Phase

Component

0x22

TCG Physical Presence execution

DXE

TCG

0xB1

TCG DXE common pass through

DXE

TCG

0xE3

First Legacy BIOS Task table for legacy reset

LBT

Core

0x20

Verify that DRAM refresh is operating by polling the refresh bit in PORTB.

LBT

Core

0xDA

Dummy PCIE Init entry, now handled by driver

LBT

Core

0x29

PMM (POST Memory Manager) init

LBT

Core

0xE5

WHEA init

LBT

Core

0x33

PDM (Post Dispatcher Manager) init

LBT

Core

0x01

IPMI init

LBT

Core

0xD8

ASF Init

LBT

Core

0x09

Set in-POST flag in CMOS that indicates we are in POST. If this bit is not cleared by postClearBootFlagJ(AEh), the TrustedCore on next boot determines that the current configuration caused POST to fail and uses default values for configuration.

LBT

Core

0x2B

Enhanced CMOS init

LBT

Core

0xE0

EFI Variable Init

LBT

Core

0xC1

PEM (Post Error Manager) init

LBT

Core

0x3B

Debug Service Init (ROM Polit)

LBT

Core

0xDC

POST Update Error

LBT

Core

0x3A

Autosize external cache and program cache size for enabling later in POST.

LBT

Core

0x0B

Enable CPU cache. Set bits in cmos related to cache.

LBT

Core

0x0F

Enable the local bus IDE as primary or secondary depending on other drives detected.

LBT

Core

0x10

Initialize Power Management.

LBT

Core

0x14

Verify that the 8742 keyboard controller is responding. Send a self-test command to the 8742 and wait for results. Also read the switch inputs from the 8742 and write the keyboard controller command byte.

LBT

Core

0x1A

Initialize DMA command register with these settings:

  1. Memory to memory disabled
  2. Channel 0 hold address disabled
  3. Controller enabled
  4. Normal timing
  5. Fixed priority
  6. Late write selection
  7. DREQ sense active
  8. DACK sense active low. Initialize

LBT

Core

0x22

Reset the keyboard.

LBT

Core

0x40

Test A20 line

LBT

Core

0x67

Quick initialization of all Application Processors in a multiprocessor system

LBT

Core

0x32

Compute CPU speed.

LBT

Core

0x69

Initialize the handler for SMM.

LBT

Core

POST Code

Function

Phase

Component

0x6B

If CMOS is bad, load Custom Defaults from flash into CMOS. If successful, reboot.

LBT

Core

0x3C

If CMOS is valid, load chipset registers with values from CMOS, otherwise load defaults and display Setup prompt. If Auto Configuration is enabled, always load the chipset registers with the Setup defaults (Rel 6.0).

LBT

Core

0x3D

Load alternate registers with CMOS values

LBT

Core

0x42

Initialize interrupt vectors 0 thru 77h

LBT

Core

0x46

Verify the ROM copyright notice

LBT

Core

0x45

Initialize all motherboard devices.

LBT

Core

0x49

  1. Size the PCI bus topology and set bridge bus numbers.
  2. Set the system max bus number.
  3. Write a 0 to the command register of every PCI device.
  4. Write a 0 to all 6 base registers in every PCI device.
  5. Write a -1 to the status register of every PC

LBT

Core

0xC6

Initialize note dock

LBT

Core

0xC5

PnPnd dual CMOS (optional)

LBT

Core

0x48

Verify that the equipment specified in the CMOS matches the hardware currently installed. If the monitor type is set to 00 then a video ROM must exist. If the monitor type is 1 or 2 set the video switch to CGA. If monitor type 3, set the video switch to m

LBT

Core

0xD1

Initialize BIOS stack

LBT

Core

0xD3

Setup E820h and WAD memory map

LBT

Core

0x24

Set segment-register addressability to 4 GB

LBT

Core

0xCC

Redirect Int 10h to enable target board to use a remote serial video (PICO BIOS).

LBT

Core

0x8A

Initialize Extended BIOS Data Area and initialize the mouse.

LBT

Core

0x9D

Initialize Security Engine.

LBT

Core

0x55

USB Initialization

LBT

Core

0x52

Verify keyboard reset.

LBT

Core

0x54

Initialize keystroke clicker if enabled in Setup.

LBT

Core

0x76

Check status bits for keyboard-related failures. Display error messages on the screen.

LBT

Core

0x4A

Initialize all video adapters in system

LBT

Core

0x4C

Shadow video BIOS ROM if specified by Setup, and CMOS is valid and the previous boot was OK.

LBT

Core

0x59

Register POST Display Services, fonts, and languages with the POST Dispatch Manager.

LBT

Core

0x57

Initialize 1394 Firewire

LBT

Core

0xD6

Initialize PC card

LBT

Core

0x58

Test for unexpected interrupts. First do an STI for hot interrupts. Secondly, test the NMI for an unexpected interrupt. Thirdly, enable the parity checkers and read from memory, checking for an unexpected interrupt.

LBT

Core

0x3F

ROMPolit memory init

LBT

Core

0xC4

Install the IRQ vectors (Sever Hotkey)

LBT

Core

POST Code

Function

Phase

Component

0x7C

Initialize the hardware interrupt vectors from 08 to 0F and from 70h to 77H. Also set the interrupt vectors from 60h to 66H to zero.

LBT

Core

0x41

ROM Pilot Init

LBT

Core

0x4B

Initialize QuietBoot if it is installed. Enable both keyboard and timer interrupts (IRQ0 and IRQ1). If your POST tasks require interrupts off, preserve them with a PUSHF and CLI at the beginning and a POPF at the end. If you change the PIC, preserve the e

LBT

Core

0xDE

Initialize and UNDI ROM (fro remote flash)

LBT

Core

0xC6

Initial and install console for UCR

LBT

Core

0x4E

Display copyright notice.

LBT

Core

0xD4

Get CPU branding string

LBT

Core

0x50

Display CPU type and speed

LBT

Core

0xC9

pretask before EISA init

LBT

Core

0x51

EISA Init

LBT

Core

0x5A

Display prompt "Press F2 to enter SETUP"

LBT

Core

0x5B

Disable CPU cache.

LBT

Core

0x5C

Test RAM between 512K and 640K.

LBT

Core

0x60

Determine and test the amount of extended memory available. Determine if memory exists by writing to a few strategic locations and see if the data can be read back. If so, perform an address-line test and a RAM test on the memory. Save the total extended

LBT

Core

0x62

The amount of memory available. This test is dependent on the processor, since the test will vary depending on the width of memory (16 or 32 bits). This test will also use A20 as the skew address to prevent corruption of the system memory.

LBT

Core

0x64

Jump to UserPatch1.

LBT

Core

0x66

Set cache registers to their CMOS values if CMOS is valid, unless auto configuration is enabled, in which case load cache registers from the Setup default table.

LBT

Core

0x68

Enable external cache and CPU cache if present. Configure non-cacheable regions if necessary.

LBT

Core

0x6A

Display external cache size on the screen if it is non-zero.

LBT

Core

0x6C

Display shadow message

LBT

Core

0xCA

post EISA init

LBT

Core

0x70

Check flags in CMOS and in the TrustedCore data area for errors detected during POST. Display error messages on the screen.

LBT

Core

0x72

Check status bits to see if configuration problems were detected. If so, display error messages on the screen.

LBT

Core

0x4F

Initialize MultiBoot. Allocate memory for old and new MultiBoot history tables.

LBT

Core

0xCD

Reclaim console vector after HW vectors initialized.

LBT

Core

0x7D

Initialize Intelligent System Monitoring.

LBT

Core

POST Code

Function

Phase

Component

0x7E

The Coprocessor initialization test. Use the floating point instructions to determine if a coprocessor exists instead of the ET bit in CR0.

LBT

Core

0xC1

Check Boot Type (Server BIOS)

LBT

Core

0x80

Disable onboard COM and LPT ports before testing for presence of external I/O devices.

LBT

Core

0xCA

Redirect Int 15h to enable target board to use remote keyboard (PICO BIOS).

LBT

Core

0x88

Initialize interrupt controller.

LBT

Core

0x81

Run late device initialization routines.

LBT

Core

0x87

Initialize motherboard configurable devices.

LBT

Core

0x85

Display any ESCD read errors and configure all PnP ISA devices.

LBT

Core

0x82

Test and identify RS232 ports.

LBT

Core

0x84

Test and identify parallel ports.

LBT

Core

0x86

Initialize onboard I/O and BDA according to CMOS and presence of external devices.

LBT

Core

0x83

Configure Fisk Disk Controller.

LBT

Core

0xCE

Initialize digitizer device and display installed message if successful.

LBT

Core

0x89

Enable non-maskable interrupts.

LBT

Core

0x8C

Initialize both of the floppy disks and display an error message if failure was detected. Check both drives to establish the appropriate diskette types in the TrustedCore data area

LBT

Core

0xCB

Redirect Int 13h to Memory Technologies Devices such as ROM, RAM, PCMCIA, and serial disk (PICO BIOS).

LBT

Core

0xCD

Remap I/O and memory address space for PCMCIA (PICO BIOS).

LBT

Core

0x90

Initialize hard-disk controller. If the CMOS ram is valid and intact, and fixed disks are defined, call the fixed disk init routine to initialize the fixed disk system and take over the appropriate interrupt vectors.

LBT

Core

0x8B

Setup interrupt vector and present bit in Equipment byte.

LBT

Core

0x95

  1. Check CMOS for CD-ROM drive present
  2. Activate the drive by checking for media present
  3. Check sector 11h (17) for Boot Record Volume Descriptor
  4. Check the boot catalog for validity
  5. Pick a boot entry
  6. Create a Specification Packet

LBT

Core

0x92

Jump to UserPatch2.

LBT

Core

0xB6

If password on boot is enabled, a call is made to Setup to check password. If the user does not enter a valid password, Setup does not return.

LBT

Core

0x98

Search for option ROMs. Rom scan the area from C800h for a length of BCP_ROM_Scan_Size (or to E000h by default) on every 2K boundary, looking for add on cards that need initialization.

LBT

Core

0x93

Build the MPTABLE for multi-processor boards

LBT

Core

POST Code

Function

Phase

Component

0xD9

IPMI late init

LBT

Core

0x9C

Set up Power Management. Initiate power -management state machine.

LBT

Core

0xC7

Late note dock init

LBT

Core

0x9E

Enable hardware interrupts

LBT

Core

0xA0

Setup time tick for current date/time

LBT

Core

0xA2

Setup Numlock indicator. Display a message if key switch is locked.

LBT

Core

0xA4

Initialize typematic rate

LBT

Core

0xDB

StrongROM Test

LBT

Core

0xE2

OEM security key test

LBT

Core

0xC2

Write PEM errors.

LBT

Core

0xBA

Initialize the SMBIOS header and sub-structures.

LBT

Core

0xC3

Display PEM errors.

LBT

Core

0xA8

Overwrite the "Press F2 for Setup" prompt with spaces, erasing it from the screen.

LBT

Core

0xAA

Scan the key buffer to see if the F2 key was struck after keyboard interrupts were enabled. If an F2 keystroke is found, set a flag.

LBT

Core

0xE1

Start Periodic Timer (TC Subscribe)

LBT

Core

0xAC

Check if "Enter SETUP" is pressed.

LBT

Core

0x8F

Count the number of ATA drives in the system and update the number in bdaFdiskcount.

LBT

Core

0x91

Configure the local bus IDE timing register based on the drives attached to it.

LBT

Core

0x9F

Check the total number of Fast Disks (ATA and SCSI) and update the bdaFdiskCount.

LBT

Core

0xD7

Check if FirstWare HPA exists

LBT

Core

0xAE

Clear ConfigFailedBit and InPostBit in CMOS.

LBT

Core

0xB0

Check for errors and decide if needs to run Setup.

LBT

Core

0xB2

Change status bits in CMOS and/or the TrustedCore data area to reflect the fact that POST is complete.

LBT

Core

0xB5

Fade out OEM Logo or post string

LBT

Core

0xC5

End hotkey detection (Server BIOS)

LBT

Core 16

0xBE

If BCP option is enabled, clear the screen before booting.

LBT

Core

0xB6

If password on boot is enabled, a call is made to Setup to check password. If the user does not enter a valid password, Setup does not return.

LBT

Core

0xBC

Clear parity-error latch

LBT

Core

0xB7

Initialize ACPI BIOS.

LBT

Core

0x9B

Enable CPU management (Geyserville I)

LBT

Core

0xBD

Display Boot First menu if MultiBoot is installed and hotkey pressed.

LBT

Core

0xBF

Check virus and backup reminders.

LBT

Core

0x97

Create pointer to MP table in Extended BDA.

LBT

Core

POST Code

Function

Phase

Component

0x99

Check support status for Self-Monitoring Analysis Reporting Technology (disk-failure warning).

LBT

Core

0xB1

Unload ROM Pilot

LBT

Core

0xDD

Perform remote flash if requested

LBT

Core

0xC7

If UCR redirection is installed, remove display manager and unhookINT10

LBT

Core

0XDF

Shutdown the PXE UNDI code

LBT

Core

0xB3

Store enhanced CMOS values in non-volatile area

LBT

Core

0xE4

Last Legacy BIOS Task before hand off to UEFI/DXE

LBT

Core

0xB9

Clear all screen graphics before booting.

bootLegacy

Core

0xC0

INT19 entry for legacy boot

bootLegacy

Core

0xEF

Invalid AP #

SDXE

Core

0xEF

Non-Yohna and non-Modem class CPU found for SDXE (getTSCFreq)

SDXE

Core

0xEE

AP cannot synch BSP in SDXE (syncWithBSP)

SDXE

Core

0xEE

BSP cannot synch w/ AP in SDXE (syncWithAP)

SDXE

Core

Jumper and Connector Locations

Chapter 5

Top View

The Ultimate Computer Repair Guide

The Ultimate Computer Repair Guide

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