Chipset POST Codes

POST Code

Function

Phase

Component

0xA0

MRC Entry

PEI

chipset/MRC

0x01

Enable MCHBAR

PEI

chipset/MRC

0x02

Check ME existence

PEI

chipset/MRC

0x03

Check for DRAM initialization interrupt and reset fail

PEI

chipset/MRC

0x04

Determine the system Memory type based on first populated socket

PEI

chipset/MRC

0x05

Verify all DIMMs are DDR2 and SO-DIMMS, which are unbuffered

PEI

chipset/MRC

0x06

Verify all DIMMs are Non-ECC

PEI

chipset/MRC

0x07

Verify all DIMMs are single or double sided and not mixed

PEI

chipset/MRC

0x08

Verify all DIMMs are x8 or x16 width

PEI

chipset/MRC

0x09

Calculate number of Row and Column bits

PEI

chipset/MRC

0x10

Calculate number of banks for each DIMM

PEI

chipset/MRC

0x11

Determine raw card type

PEI

chipset/MRC

0x12

Find a common CAS latency between the DIMMS and the MCH

PEI

chipset/MRC

0x13

Determine the memory frequency and CAS latency to program

PEI

chipset/MRC

0x14

Determine the smallest common timing value for all DIMMS

PEI

chipset/MRC

0x17

Power management resume

PEI

chipset/MRC

0x18

Program DRAM type (DDR2/DDR3) and Power up sequence

PEI

chipset/MRC

0x19

Program the correct system memory frequency

PEI

chipset/MRC

0x20

Program the correct Graphics memory frequency

PEI

chipset/MRC

0x21

Early DRC initialization

PEI

chipset/MRC

0x22

Program the DRAM Row Attributes and DRAM Row Boundary registers PRE JEDEC.

PEI

chipset/MRC

0x23

Program the RCOMP SRAM registers

PEI

chipset/MRC

0x24

Program DRAM type (DDR2/DDR3) and Power up sequence

PEI

chipset/MRC

0x25

Program the DRAM Timing

PEI

chipset/MRC

0x26

Program the DRAM Bank Architecture register

PEI

chipset/MRC

0x27

Enable all clocks on populated rows

PEI

chipset/MRC

0x28

Program MCH ODT

PEI

chipset/MRC

0x29

Program tRD

PEI

chipset/MRC

0x30

Miscellaneous Pre JEDEC steps

PEI

chipset/MRC

0x31

Program clock crossing registers

PEI

chipset/MRC

0x32

Program the Egress port timings

PEI

chipset/MRC

0x33

Program the Memory IO registers

PEI

chipset/MRC

0x34

Perform steps required before JEDEC

PEI

chipset/MRC

0x35

Perform JEDEC memory initialization for all memory rows

PEI

chipset/MRC

0x36

Setup DRAM control register for normal operation and enable

PEI

chipset/MRC

0x37

Do ZQ calibration for DDR3

PEI

chipset/MRC

0x38

Perform final Dra/Drb programming, Set the mode of operation for the memory channels

PEI

chipset/MRC

POST Code

Function

Phase

Component

0x39

Set Enhanced addressing mode for each channel

PEI

chipset/MRC

0x40

Perform steps required after JEDEC init

PEI

chipset/MRC

0x41

Program the receive enable reference timing control register

PEI

chipset/MRC

0x42

Post receive enable initialization

PEI

chipset/MRC

0x43

Enable sense amps. Reset read/write DQS pointers

PEI

chipset/MRC

0x44

Perform ME steps

PEI

chipset/MRC

0x45

Clear DRAM initialization bit in the ICH.

PEI

chipset/MRC

0x46

Program Thermal Management

PEI

chipset/MRC

0x47

Program TS on DIMM

PEI

chipset/MRC

0x48

Program TS on Board

PEI

chipset/MRC

0xAF

Exit MRC

PEI

chipset/MRC

0xE0

#define MEM_ERR_BAD_DIMM (S11)

PEI

chipset/MRC

0xE1

#define MEM_ERR_ECC_DIMM (S06)

PEI

chipset/MRC

0xE2

#define MEM_ERR_SIDES (S07)

PEI

chipset/MRC

0xE3

#define MEM_ERR_WIDTH (S08, S10)

PEI

chipset/MRC

0xE4

#define MEM_ERR_TRFC (FindTrasTrpTrcd)

PEI

chipset/MRC

0xE5

#define MEM_ERR_CAS_LATENCY (S12, S13)

PEI

chipset/MRC

0xE6

#define MEM_ERR_REFRESH (ProgDrt)

PEI

chipset/MRC

0xE7

#define MEM_ERR_BL8 (S14)

PEI

chipset/MRC

0xE9

#define MEM_ERR_FREQUENCY (findTCLTacTClk, S13, S12, ProgramGraphicsFrequency, ProgMchOdt, GetPlatformData)

PEI

chipset/MRC

0xEA

#define MEM_ERR_SIZE (S14)

PEI

chipset/MRC

0xEC

#define MEM_ERR_TRAS (FindTrasTrpTrcd)

PEI

chipset/MRC

0xED

#define MEM_ERR_TRP (FindTrasTrpTrcd)

PEI

chipset/MRC

0xEE

#define MEM_ERR_TRCD (FindTrasTrpTrcd)

PEI

chipset/MRC

0xEF

#define MEM_ERR_TWR (FindTrasTrpTrcd)

PEI

chipset/MRC

0xF0

#define MEM_ERR_RCVEN_FINDLOW (CalibrateRcvenForGroup)

PEI

chipset/MRC

0xF1

#define MEM_ERR_RCVEN_FINDEDGE (CalibrateRcvenForGroup)

PEI

chipset/MRC

0xF2

#define MEM_ERR_RCVEN_FINDPREAMBLE (CalibrateRcvenForGroup)

PEI

chipset/MRC

0xF6

#define MEM_ERR_RCVEN_PREAMBLEEDGE (CalibrateRcvenForGroup)

PEI

chipset/MRC

0xF3

#define MEM_ERR_RCVEN_FINDCENTER (CalibrateRcvenForGroup)

PEI

chipset/MRC

0xF4

#define MEM_ERR_TYPE (S11, S04)

PEI

chipset/MRC

0xF5

#define MEM_ERR_RAWCARD (S11)

PEI

chipset/MRC

0xFA

#define MEM_ERR_SFF (ProgWrioDll)

PEI

chipset/MRC

0xFB

#define MEM_ERR_THERMAL (ProgramThrottling)

PEI

chipset/MRC

0xA0xx

Launch BIOS ACMSclean

PEI

chipset/MRC

0xA4xx

Launch BIOS ACMScheck

PEI

chipset/MRC

0xE5

Wait for ME ready

DXE

HECI/iAMT

0xE6

ME Ready

DXE

HECI/iAMT

Was this article helpful?

0 0
The Ultimate Computer Repair Guide

The Ultimate Computer Repair Guide

Read how to maintain and repair any desktop and laptop computer. This Ebook has articles with photos and videos that show detailed step by step pc repair and maintenance procedures. There are many links to online videos that explain how you can build, maintain, speed up, clean, and repair your computer yourself. Put the money that you were going to pay the PC Tech in your own pocket.

Get My Free Ebook


Responses

  • lotta
    How to determine acer aspire one chipset?
    9 years ago

Post a comment